Extended publicity may well have an affect on the trustworthiness of your gear

The AT24C08A only employs the A2 enter for hardwire addressing and a complete of two 8K gadgets may be dealt with with a solitary bus process. The A0 and A1 pins aren't any connects and will be linked to floor. The AT24C16A won't use the machine address pins, which restrictions the number of products with a solitary bus to 1.
The A0, A1 and A2 pins are not any connects and might be related to floor. Generate Defend (WP): The AT24C01A/02/04/08A/16A contains a Publish Safeguard pin that gives components details protection. The Publish Protect pin permits regular Read/Write functions when related to ground (GND).When the Write Safeguard pin is connected to VCC, the generate safety aspect is enabled and operates as demonstrated in Desk two. Desk two.
Compose Safeguard Memory Business AT24C01A, 1K SERIAL EEPROM: Internally arranged with 16 pages of eight bytes each individual, the 1K demands a 7-bit data phrase handle for random phrase addressing.
AT24C02, 2K SERIAL EEPROM: Internally structured with 32 pages of 8 bytes each, the 2K needs an 8-bit details term handle for random word addressing. AT24C04, 4K SERIAL EEPROM: Internally arranged with 32 internet pages of 16 bytes every single, the 4K demands a 9-bit info phrase address for random phrase addressing.
AT24C08A, 8K SERIAL EEPROM: Internally arranged with sixty four pages of 16 bytes every single, the 8K needs a 10-bit info word address for random word addressing.
AT24C16A, 16K SERIAL EEPROM: Internally structured with 128 web pages of 16 bytes every single, the 16K calls for an 11-bit knowledge word deal with for random term addressing.

Initialization of site writes is the same as initialization of byte writes

Generate Functions BYTE Write: A compose operation needs an 8-bit information term deal with adhering to thedevice deal with word and acknowledgment. Upon receipt of the tackle, the EEPROM will once again reply that has a zero and afterwards clock in the to start with 8-bit info phrase.
Followingreceipt of the 8-bit details term, the EEPROM will output a zero plus the addressingdevice, like a microcontroller, should terminate the produce sequence which has a stop condi-tion. At this time the EEPROM enters an internally timed publish cycle, tWR, to thenonvolatile memory.
All inputs are disabled through this generate cycle along with the EEPROM willnot answer until eventually the create is comprehensive (seek advice from Figure 2).Page Generate: The 1K/2K EEPROM is able of an 8-byte web site write, along with the 4K, 8Kand 16K equipment are capable of 16-byte site writes.
A web page compose is initiated the same as a byte generate, even so the microcontroller will not senda end condition right after the initial knowledge word is clocked in. In its place, soon after the EEPROMacknowledges receipt of the initially details term, the microcontroller can transmit nearly seven(1K/2K) or fifteen (4K, 8K, 16K) a lot more information phrases.
The EEPROM will react with a zeroafter each individual information phrase obtained. The microcontroller must terminate the web page writesequence which has a prevent problem (make reference to Figure three).The information word deal with decrease 3 (1K/2K) or four (4K, 8K, 16K) bits are internallyincremented pursuing the receipt of every facts term. The upper information word address bitsare not incremented, retaining the memory site row location.
If the phrase address,internally generated, reaches the page boundary, the subsequent byte is positioned at thebeginning of the exact same site. If a lot more than eight (1K/2K) or sixteen (4K, 8K, 16K) datawords are transmitted to your EEPROM, the data phrase deal with will “roll over” and previ-ous details will probably be overwritten.

Ship a boot affliction just after the gadget tackle

Read through functions are initiated a similar way as publish operations with the exception that theread/write find bit in the gadget deal with word is about to one. There are a few examine operations:existing tackle browse, random handle browse and sequential examine.
Present Deal with Browse: The inner information word address counter maintains the lastaddress accessed over the very last browse or write procedure, incremented by a single. This addressstays legitimate in between functions as long as the chip electricity is taken care of.
The address “rollover” for the duration of read through is from the final byte with the final memory website page on the 1st byte on the initially site.The handle “roll over” throughout compose is within the final byte of the current web page to the first byte ofthe very same webpage.When the gadget deal with together with the read/write select little bit established to 1 is clocked in and acknowl-edged through the EEPROM, the present handle data phrase is serially clocked out. Themicrocontroller will not reply having an enter zero but does create a adhering to quit condi-tion.
RANDOM Read: A random study needs a “dummy” byte generate sequence to load in the dataword deal with. As soon as the gadget handle phrase and info term handle are clocked in andacknowledged by the EEPROM, the microcontroller have to generate one more start out issue.The microcontroller now initiates a recent handle read by sending a device deal with with theread/write select bit significant.
The EEPROM acknowledges the unit tackle and serially clocksout the data word. The microcontroller isn't going to reply using a zero but does create a fol-lowing stop ailment.SEQUENTIAL Go through: Sequential reads are initiated by both a latest tackle read through or maybe a ran-dom handle browse. Just after the microcontroller receives an information term, it responds with anacknowledge.
Provided that the EEPROM receives an acknowledge, it will eventually go on to incrementthe info term handle and serially clock out sequential details words and phrases. When the memoryaddress restrict is arrived at, the information phrase address will “roll over” as well as sequential go through will con-tinue. The sequential read through procedure is terminated once the microcontroller doesn't respondwith a zero but does generate a adhering to halt ailment.

Confirmation polling is ready to begin

ACKNOWLEDGE POLLING: Once the internally-timedwrite cycle has started and the EEPROM inputs are dis-abled, acknowledge polling can be initiated. This involvessending a start condition followed by the device addressword.
The read/write bit is representative of the operationdesired. Only if the internal write cycle has completed willthe EEPROM respond with a zero allowing the read orwrite sequence to continue.Read OperationsRead operations are initiated the same way as write opera-tions with the exception that the read/write select bit in thedevice address word is set to one. There are two readoperations: byte read and sequential read.
BYTE READ: A byte read is initiated with a start conditionfollowed by a 7-bit data word address and a high read bit.The AT24C01 will respond with an acknowledge and thenserially output 8 data bits. The microcontroller does notrespond with a zero but does generate a following stopcondition.
SEQUENTIAL READ: Sequential reads are initiated thesame as a byte read. After the microcontroller receives an8-bit data word, it responds with an acknowledge. As longas the EEPROM receives an acknowledge, it will continueto increment the data word address and serially clock outsequential data words.
When the memory address limit isreached, the data word address will “roll over” and thesequential read will continue. The sequential read opera-tion is terminated when the microcontroller does notrespond with an input zero but does generate a followingstop condition.